VCS
The tool vcs by Synopsys is used to compile Verilog files into an executable typically called simv. It internally uses a makefile to efficiently update the output. It is therefore possible for the output to remain unchanged.
License management
Use the +vcs+lic+wait option to enable vendor queueing.
Preemption
## Add this to your vovpreemptd/config.tcl file
VovPreemptMethod License:VCSRuntime_Net LMREMOVE
VovPreemptMethod License:VT_TestbenchRuntime LMREMOVE
- Launch a SIMV job
- Go to the machine on which the job is running
- Identify the PID of the simv process
- kill -TSTP PID_OF_SIMV
- If the simv process stops and the license has been released (check with lmstat), then your SIMV can be preempted with SIGTSTP, which would be more effective than LMREMOVE. Otherwise, stay with LMREMOVE.
Encapsulation
# This is an example capsule for vcs
# Put this in file $VOVDIR/local/capsules/vov_vcs.tcl
while { $argv != {} } {
set arg [shift]
switch -- $arg {
"-f" { VovInput [shift] }
"-o" { VovOutput -ignore_timestamp [shift] }
"-l" { VovOutput [shift] }
default {}
}
}